1. Field of the Invention
The present invention relates to an integrated circuit having a digital processor, a Viterbi decoder, and a shared memory.
2. Description of the Prior Art
Viterbi decoders are used in signal processing applications to give an improved estimate of a received digital signal sequence in the face of channel noise. For example, cellular telephones are increasingly moving to digital transmission techniques of various types. One digital standard (GSM) has been generally adopted for use in Europe, while another (IS54) is intended for use in North America, with still others under consideration. However, the nature of cellular transmission and reception, often occurring from moving vehicles or pedestrians, gives rise to a variety of channel disturbances. For example, multi-path interference exists when reflections from nearby objects causes several signals, delayed in time from the original signal, to be received. Therefore, the received digital sequence may not exactly match the transmitted sequence. The digital sequences are sent in "packets" having a desired number of digital bits, which may be fixed, or alternatively variable, in order to compensate for transmission difficulties. The above-noted standards provide various forms of Forward Error Correction (FEC), by which additional bits are included in the packets to provide a degree of redundancy in transmission, so that errors may be detected and corrected to some degree at the receiving end. The packets may contain digitized voice information or other forms of data, including computer files, video information, etc.
A Viterbi trellis decoder is one commonly used method of decoding the received packets in order to recover the transmitted sequence. That is, given the properties of the FEC encoder used, some sequences of bits are more likely than others. Therefore, the Viterbi decoder provides a MLSE (Most Likely Sequence Estimation) deconvolution output, to more accurately recover the transmitted sequence in the face of channel noise and distortion of various types. In addition to correcting errors due to random noise, a Viterbi decoder can improve receiver performance in the presence of multi-path interference, since the received digits are then not independent of one another, but correlated to some degree. The decoding of a known bit sequence can then be used to adjust the tap weights of an equalizer, which compensates for the multi-path interference. Therefore, a knowledge of the history of a received signal sequence can be used to improve the accuracy of recovering the signal sequence that was actually sent. An overview of the Viterbi decoding technique is given in "Overview of the Viterbi Algorithm", Mobile Radio Communications, R. Steele (editor), Pentech, London (1992).
In the prior art, the Viterbi decoder has been implemented in one or more integrated circuits. The control circuitry that instructs the Viterbi is implemented on one or more other integrated circuits. In some cases, the control circuitry is of limited flexibility in terms of the ease of passing instructions to the Viterbi decoder. Furthermore, the complexity of the circuit functions has hindered their economical inclusion in a single integrated circuit. It is desirable to implement a Viterbi decoder that obtains improved functionality and ease of programming, while reducing the total number of integrated circuits needed to implement the desired functionality.